A framework for solving VLSI graph layout problems

A Framework for Solving VLSI Graph Layout Problems

An efficient approach for solving layout problems

This paper offers an approach that could be useful for diverse types of layout problems or even area allocation problems. By this approach there is no need to large number of discrete variables and only by few continues variables large-scale layout problems could be solved in polynomial time. This is resulted from dividing area into discrete and continuous dimensions. Also defining decision var...

an efficient approach for solving layout problems

this paper offers an approach that could be useful for diverse types of layout problems or even area allocation problems. by this approach there is no need to large number of discrete variables and only by few continues variables large-scale layout problems could be solved in polynomial time. this is resulted from dividing area into discrete and continuous dimensions. also defining decision var...

Mathematical Programming Models for Solving Unequal-Sized Facilities Layout Problems - a Generic Search Method

 This paper present unequal-sized facilities layout solutions generated by a genetic search program named LADEGA (Layout Design using a Genetic Algorithm). The generalized quadratic assignment problem requiring pre-determined distance and material flow matrices as the input data and the continuous plane model employing a dynamic distance measure and a material flow matrix are discussed. Computa...

Preprocessing Steiner problems from VLSI layout

VLSI layout applications yield instances of the Steiner tree problem over grid graphs with holes, which are considered hard to be solved by current methods. In particular, preprocessing techniques developed for Steiner problems over general graphs are not likely to reduce signiicantly such VLSI instances. We propose a new preprocessing procedure, combining earlier ideas from the literature to m...